1. Field of the Invention
The present invention relates to a charge domain filter circuit.
2. Description of the Related Art
The miniaturization of the complementary metal oxide semiconductor (CMOS) process has the disadvantage that using known circuit technology to implement the RF circuit to reduce the power supply voltage reduces the dynamic range of the signal amplitude, because there is little voltage allowance. On the other hand, because miniaturization raises the cutoff frequency of the transistor, it is suitable for operations such as high-speed switching that must be performed with precise timing. Another advantage is that, because the lithography is performed with high precision, the capacitance ratios of capacitors can be specified accurately.
Digital RF technology is a technology that resolves the disadvantages that the miniaturization of the CMOS process engenders for the RF circuit and converts them to advantages. The main circuit in a discrete time receiver (DTR), in which digital RF technology is used for the receiver, is a charge domain filter. The charge domain filter includes a capacitor that accumulates and discharges a charge on a specified cycle. In the charge domain filter circuit, the filter is configured from only a transconductor and a switch, so it is capable of directly sampling and filtering RF signals in the gigahertz band.
It has been proposed that the filter characteristics of the charge domain filter can be made reconfigurable by varying the frequencies and waveforms of the filter's clock signals (refer to R. Bagheri et al., “An 800 MHz to 5 GHz Software-Defined Radio Receiver in 90 nm CMOS,” in IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, February 2006, pp. 480-481). FIG. 20 is an explanatory figure that shows a known charge domain filter circuit, proposed by Bagheri et al., that has reconfigurable filter characteristics. FIGS. 21A, 21B and 21C are explanatory figures that show waveforms of clock signals that are input to a charge domain filter circuit 10 in FIG. 20. The clock signals shown in FIGS. 21A, 21B and 21C are respectively input to the various switches shown in the charge domain filter circuit 10 in FIG. 20. Each switch is on when the corresponding clock signal (indicated by the characters next to the switch) is high.
The charge domain filter circuit 10 shown in FIG. 20 is a sinc filter that is capable of switching its decimation ratio to 2 and 3. The charge domain filter circuit 10 shown in FIG. 20 operates such that the decimation ratio becomes 2 when the clock signals shown in FIG. 21B are input, and the decimation ratio becomes 3 when the clock signals shown in FIG. 21C are input. The charge domain filter circuit 10 thus has reconfigurable filter characteristics.
The operation of the charge domain filter circuit 10 will be explained. Four capacitors in the charge domain filter circuit 10 accumulate and discharge charges in temporal order. Taking a capacitor C1 as an example, when a clock signal Ψ1,r becomes high, the two terminals of the capacitor C1 are short-circuited and the charge is reset. When a clock signal Ψ1 becomes high, a charge is accumulated from the input terminal. When a clock signal K1 becomes high, the charge is discharged from the capacitor C1 to the output terminal.
In a case where the decimation ratio is 2, an operation is repeated in which the charges of capacitors C1 and C2 are discharged simultaneously by clock signals K1 and K2, and the charges of capacitors C3 and C4 are discharged simultaneously by clock signals K3 and K4. The clock signals K1 to K4 therefore become repetitions of simple rectangular waves, as shown in FIG. 21B.
In contrast, in a case where the decimation ratio is 3, when the clock signal Ψ1 becomes high, the charges of the capacitors C2, C3, and C4 are discharged simultaneously by clock signals K2, K3, and K4. When a clock signal Ψ4 becomes high, the charges of the capacitors C1, C2, and C3 are discharged simultaneously by clock signals K1, K2, and K3. When a clock signal Ψ3 becomes high, the charges of the capacitors C1, C2, and C4 are discharged simultaneously by clock signals K1, K2, and K4. When a clock signal Ψ2 becomes high, the charges of the capacitors C1, C3, and C4 are discharged simultaneously by clock signals K1, K3, and K4. The clock signals K1 to K4 therefore become repetitions of irregular rectangular waves with long cycles, as shown in FIG. 21C.